Implement a 4-bit unsigned magnitude comparator. Ports: - `a` — input, 4 bits (`a[3:0]`) - `b` — input, 4 bits (`b[3:0]`) - `gt` — output, 1 bit — asserted (1) when `a > b` - `lt` — output, 1 bit — asserted (1) when `a < b` - `eq` — output, 1 bit — asserted (1) when `a == b` Exactly one of `gt`, `lt`, `eq` is 1 at any given time (they are mutually exclusive and collectively exhaustive over all possible `a`, `b` pairs). This circuit is purely combinational — all three outputs must update immediately whenever `a` or `b` changes, with no clock and no internal state involved. Both `a` and `b` are treated as unsigned 4-bit values (range 0–15).