Implement a 4-bit synchronous up-counter with synchronous reset and a count-enable input. The module has the following ports: `clk` (clock, 1 bit), `rst` (synchronous, active-high reset, 1 bit), `en` (active-high count-enable, 1 bit), and `count` (4-bit registered output, `count[3:0]`). On every rising edge of `clk`, the counter behaves as follows, in priority order: 1. If `rst` is high, `count` must synchronously reset to `4'b0000`, regardless of the value of `en`. Reset always takes priority over enable. 2. Else, if `en` is high, `count` increments by 1. When `count` is at its maximum value `4'b1111` (15), the next enabled clock edge must wrap it around to `4'b0000`. 3. Else (both `rst` and `en` are low), `count` holds its current value — no change on that clock edge. All behavior is synchronous: nothing should change except on the rising edge of `clk`. There is no asynchronous reset and no combinational path from inputs to `count`. Port summary: - `clk` — input, 1 bit, clock - `rst` — input, 1 bit, synchronous active-high reset - `en` — input, 1 bit, active-high count enable - `count` — output, 4 bits, current counter value