Implement an 8-bit maximal-length linear feedback shift register (LFSR). LFSRs are widely used in industry for pseudo-random pattern generation, data scrambling/whitening, and built-in self-test (BIST) — this is a very common interview topic for anyone working on SerDes, test infrastructure, or RNG hardware. Ports: - `clk` — input, 1 bit, clock - `rst` — input, 1 bit, synchronous active-high reset - `load` — input, 1 bit, synchronous load enable - `seed_in` — input, 8 bits (`seed_in[7:0]`), value loaded when `load` is asserted - `lfsr_out` — output, 8 bits (`lfsr_out[7:0]`), registered, current LFSR state On every rising edge of `clk`: 1. If `rst` is high, `lfsr_out` synchronously loads the fixed value `8'h01` (a guaranteed-nonzero default state). Reset overrides `load` entirely if both are asserted on the same edge. 2. Else if `load` is high, `lfsr_out` synchronously loads `seed_in` directly, regardless of its previous value. (The testbench will only ever load a nonzero seed — an all-zero state is a permanent lock-up state for this LFSR architecture and is intentionally out of scope.) 3. Else, `lfsr_out` advances by one shift step using the following **exact** feedback formula: - `feedback = lfsr_out[7] ^ lfsr_out[2] ^ lfsr_out[1] ^ lfsr_out[0]` - `lfsr_out <= {feedback, lfsr_out[7:1]}` (shift right by one bit; the new feedback bit is inserted at the MSB, and the old bit 0 is discarded) This exact tap configuration (bits 7, 2, 1, 0) is a verified maximal-length configuration for an 8-bit Fibonacci LFSR: starting from any nonzero seed, it visits all 255 nonzero 8-bit states exactly once before returning to its starting value, with `8'h00` itself being the only excluded (lock-up) state. Implementations must match this exact tap formula bit-for-bit — alternate (but plausible-looking) tap choices will desynchronize from the expected sequence after only one or two shifts.