Implement a configurable Pulse Width Modulation (PWM) generator. PWM is used everywhere in industry — motor speed control, LED brightness control, DC-DC converters, audio DACs, and servo control. Being able to design a parameterizable PWM block from scratch is a common practical interview question. Ports: - `clk` — input, 1 bit, clock - `rst` — input, 1 bit, synchronous active-high reset - `duty` — input, 8 bits (`duty[7:0]`), number of clock cycles `pwm_out` is high per period (0–255) - `period` — input, 8 bits (`period[7:0]`), total length of one PWM cycle in clock cycles (1–255); the caller is responsible for ensuring `duty <= period` - `pwm_out` — output, 1 bit, the PWM signal — combinational function of internal counter Internally, maintain an 8-bit counter that advances on every rising edge of `clk`: 1. If `rst` is high, the counter synchronously resets to `8'h00`. Reset overrides normal counting. 2. Otherwise, if the counter equals `period - 1`, it wraps back to `8'h00` on the next edge. Otherwise it increments by 1. `pwm_out` is a **combinational** (non-registered) output: `pwm_out = 1` when `duty != 0` and `counter < duty`; otherwise `pwm_out = 0`. In other words, `pwm_out` is high for the first `duty` counter values (0 through `duty-1`) of each period, and low for the remaining `period - duty` counter values. Special cases: if `duty = 0`, `pwm_out` is always 0 (0% duty cycle). If `duty = period`, `pwm_out` is always 1 (100% duty cycle). Both `duty` and `period` may be changed between resets and the output will adjust accordingly, starting from the next counter value.