Implement a D latch with active-high enable. Understanding the difference between a latch (level-sensitive) and a flip-flop (edge-triggered) is a fundamental digital design interview topic — latches are often introduced unintentionally by incomplete case/if statements in Verilog, so recognizing and deliberately building one is important. Ports: - `en` — input, 1 bit, active-high enable (transparent gate) - `d` — input, 1 bit, data input - `q` — output, 1 bit, data output (latched value) - `q_n` — output, 1 bit, complement of `q` (always the bitwise inverse of `q`) Behavior: When `en` is high, the latch is **transparent**: `q` immediately and continuously follows `d`. Any change on `d` while `en` is high is reflected on `q` with no clock edge required. When `en` goes low, the latch **holds**: `q` freezes at whatever value `d` had at the moment `en` went low. Changes on `d` while `en` is low have no effect on `q` — `q` holds its state until `en` goes high again. `q_n` is the bitwise complement of `q` at all times — it is a purely combinational wire, not a separately stored value. This circuit is intentionally **not** clocked. There is no `clk` port. The correct Verilog implementation uses a combinational `always @(*)` block with a conditional that only drives `q` when `en` is high and omits an `else` branch — this incomplete assignment is exactly what causes the Verilog synthesizer to infer a latch.