Implement an 8-bit even-parity checker. Ports: - `data` — input, 8 bits (`data[7:0]`), the data word to check - `parity_bit` — input, 1 bit, the parity bit that was transmitted alongside `data` - `error` — output, 1 bit — asserted (1) when the total number of 1-bits across `{parity_bit, data}` (all 9 bits combined) is odd, meaning even parity has been violated; 0 when the total number of 1-bits is even (parity holds) This circuit assumes the even-parity convention: a correctly-encoded `{parity_bit, data}` pair should always contain an even number of 1s in total. If `data` contains an odd number of 1-bits, a correctly generated `parity_bit` would be 1 (making the 9-bit total even); if `data` contains an even number of 1-bits, a correctly generated `parity_bit` would be 0. `error` must be computed purely combinationally — it should update immediately whenever `data` or `parity_bit` changes, with no clock and no internal state involved.