Implement an 8-entry, 8-bit register file with two asynchronous read ports and one synchronous write port — the fundamental storage element inside every processor's datapath. This is a standard building block asked about in nearly every CPU/ASIC design interview. Ports: - `clk` — input, 1 bit, clock - `we` — input, 1 bit, write enable - `waddr` — input, 3 bits (`waddr[2:0]`), write address (selects one of 8 registers: 0–7) - `wdata` — input, 8 bits (`wdata[7:0]`), data to write - `raddr1` — input, 3 bits (`raddr1[2:0]`), read address for port 1 - `raddr2` — input, 3 bits (`raddr2[2:0]`), read address for port 2 - `rdata1` — output, 8 bits (`rdata1[7:0]`), data read from port 1 - `rdata2` — output, 8 bits (`rdata2[7:0]`), data read from port 2 Behavior: **Writes** are synchronous: on the rising edge of `clk`, if `we` is high and `waddr != 0`, the value on `wdata` is stored into register `waddr`. Writes with `we` low are silently ignored. Writes to address 0 are always silently ignored — register 0 is hardwired to the value `8'h00` and cannot be overwritten under any circumstances. **Reads** are asynchronous (combinational): `rdata1` and `rdata2` continuously reflect the current contents of the registers at `raddr1` and `raddr2` respectively, with no clock edge required. A change to `raddr1` or `raddr2` is immediately reflected on the corresponding `rdata` output. Reading register 0 always returns `8'h00`. **Read-during-write**: the two read ports see the OLD (pre-write) value of a register on the same cycle that a write to that register occurs — the write does not take effect combinationally. The new value is only visible on `rdata` starting from the next cycle after the write. This is the standard "registered write, async read" behavior of most FPGA block RAM and synthesized register files. There is no reset port. The initial contents of registers 1–7 are undefined and the testbench will always write a register before reading it.