Design a synchronous FIFO (First-In-First-Out) buffer that stores up to 8 entries, each 8 bits wide. Ports: - `clk` — input, 1 bit, clock - `rst` — input, 1 bit, synchronous active-high reset - `wr_en` — input, 1 bit, write enable - `rd_en` — input, 1 bit, read enable - `data_in` — input, 8 bits, data to write - `data_out` — output, 8 bits, registered data read from the FIFO - `full` — output, 1 bit, asserted when the FIFO holds 8 entries - `empty` — output, 1 bit, asserted when the FIFO holds 0 entries Behavior, on every rising edge of `clk`: 1. If `rst` is high, the FIFO synchronously clears: both the write and read pointers reset to 0, `empty` becomes 1, and `full` becomes 0. Reset takes priority over `wr_en`/`rd_en`. 2. Else, if `wr_en` is high and the FIFO is **not** full, `data_in` is stored at the current write location and the write pointer advances by one. If `wr_en` is high while the FIFO **is** full, the write is silently ignored — no data is overwritten and no pointer advances (no overflow corruption). 3. Else, if `rd_en` is high and the FIFO is **not** empty, the data at the current read location is driven onto `data_out` (registered — it updates the cycle *after* `rd_en` is sampled) and the read pointer advances by one. If `rd_en` is high while the FIFO **is** empty, the read is silently ignored — `data_out` does not change and no pointer advances (no underflow). 4. `wr_en` and `rd_en` can be asserted on the same clock edge. If the FIFO is neither full nor empty at that moment, **both** the write and the read happen on that same edge (the new data is stored, and the data ahead of it in the FIFO is correctly output). Internally, the FIFO must use 8 storage locations and behave as a circular buffer: writes must wrap back to location 0 after location 7, and reads must do the same, in the same order data was written (strict FIFO ordering — no reordering or overwriting of unread data). `full` and `empty` are derived combinationally from the FIFO's internal pointer state, not separately-maintained flags that could drift out of sync with the actual entry count.