Implement a UART transmitter using the standard "8N1" framing: 1 start bit, 8 data bits (LSB first), no parity bit, 1 stop bit. This module operates at the baud rate directly — i.e., `clk` in this problem already ticks once per baud period (assume any baud-rate-generation/oversampling has been handled externally), so the transmitter advances exactly one bit of the frame per rising edge of `clk` while transmitting. Ports: - `clk` — input, 1 bit, clock (one tick per baud period) - `rst` — input, 1 bit, synchronous active-high reset - `tx_start` — input, 1 bit, pulsed high for one cycle to request transmission of `tx_data` - `tx_data` — input, 8 bits (`tx_data[7:0]`), the byte to transmit, sampled when `tx_start` is asserted - `tx` — output, 1 bit, the serial output line - `tx_busy` — output, 1 bit, high while a frame is currently being transmitted, low when idle and able to accept a new `tx_start` Behavior: 1. On reset, the transmitter goes to an idle state: `tx = 1` (UART idle/idle-high convention) and `tx_busy = 0`. 2. While idle, if `tx_start` is asserted, the transmitter latches `tx_data` and begins transmitting on the very next clock edge. `tx_busy` becomes 1 as soon as transmission begins and stays 1 for the entire 10-bit frame. 3. The 10-bit frame, one bit per clock cycle, in order, is: start bit (`0`), then `tx_data[0]`, `tx_data[1]`, ..., `tx_data[7]` (LSB first), then stop bit (`1`). 4. `tx_start` must be ignored while `tx_busy` is high (i.e., while a frame is in progress) — the transmitter does not interrupt an in-progress frame to start a new one. 5. After the stop bit is driven, on the following clock edge `tx_busy` returns to 0, `tx` returns to (and remains at) the idle value `1`, and the transmitter is ready to accept a new `tx_start`. All transitions are synchronous to `clk`. There is no need to model setup/hold timing beyond the per-cycle bit advancement described above.